Power Efficient Time Domain Analog to Digital Conversion and PVT Compensated Subthreshold Architectures

Abstract

This thesis facilitates the design challenges of analog and mixed-signal circuits in deep sub-micron technology. In this regard, the design of two analog multiplication architectures is proposed. The process, voltage, temperature (PVT) effect was implicitly eliminated by compressing/expanding technique. The architectures can be configured to generate division, inverse, scaling and other analog functions. The theoretical analysis has been demonstrated by post-layout extraction results in 0.18µm CMOS. The consumed power is 3µW and 0.7µW for the first and the second design, respectively. The occupied silicon area is 250 µm2. Furthermore, two techniques for VCO-based ADCs are proposed. The first technique tackles the power supply noise (PSN) using the injection locking oscillation (ILO) mechanism. Although the ILO concept has been beneficial for a variety of clock synchronizations, there has not been any design approach that takes advantage of this concept to assist the VCO-based ADC. By injecting the frequency-modulated signal into a replica VCO, within the locking range, the latter VCO frequency will always lock to the injected frequency. By digitizing the phase instead of frequency, a system level cancellation of PSN has been achieved. The design results validate the analysis with 25dB noise rejection improvement compared to the conventional VCO-based ADC. The second design proposed a preweighted technique to alleviate the nonlinearity of voltage to frequency characteristics in VCO-based ADC to achieve higher resolution. In an open loop configuration, this technique modulates the VCO’s frequency by spreading binary preweighted versions of the analog input over the VCO delay cells. As a result, each cell in the VCO produces its own corresponding delay. The results in 65m CMOS show that the voltage-to-frequency transfer characteristics is drastically improved with nonlinearity less than 1% over rail-to-rail input swing. For further area minimization, an inverse R-2R front end is proposed. A prototype was fabricated using 65nm CMOS process. It occupies an actives area of 0.03 mm2 and consumes 3.1 mA from 1 V power supply. Measurement results of linearity indicate SFDR and SNDR of 77 and 66.7 dB, respectively, over 5 MHz passband bandwidth which reveals energy less than 0.2 pJ/step in Walden figure-of-merit.