dc.contributor.author | Elsalahati, Tamer | |
dc.date.accessioned | 2017-12-15T13:38:38Z | |
dc.date.available | 2017-12-15T13:38:38Z | |
dc.date.issued | 2017-12-15T13:38:38Z | |
dc.identifier.uri | http://hdl.handle.net/10222/73527 | |
dc.description.abstract | A design technique for an asynchronous Analog-to-Digital Converter (ADC) is presented. The proposed design retains a clockless level crossing sampling technique, and then applies a Wavelet Neural Network (WNN) technique. High-level simulation results are shown for various ADC resolutions. The Signal to Noise and Distortion Ratio (SNDR) achieved for 4-bit ADC systems are presented. It has been shown that a 4-bit system with the proposed asynchronous ADC architecture using a WNN technique achieves an Effective Number Of Bits (ENOB) of up to 38 bits depending on the input frequency and resolution. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | Quantization (signal) | en_US |
dc.subject | Neural networks | en_US |
dc.subject | Wavelet transforms | en_US |
dc.subject | Delta modulation | en_US |
dc.subject | Signal resolution | en_US |
dc.subject | Wavelet Neural Networks | en_US |
dc.subject | Continuous Time | en_US |
dc.subject | Clockless ADC | en_US |
dc.subject | Level Crossing ADC | en_US |
dc.title | High Precision Clock-Less ADC Using Wavelet Neural Networks | en_US |
dc.type | Thesis | en_US |
dc.date.defence | 2017-12-05 | |
dc.contributor.department | Department of Electrical & Computer Engineering | en_US |
dc.contributor.degree | Master of Applied Science | en_US |
dc.contributor.external-examiner | NA | en_US |
dc.contributor.graduate-coordinator | Dr. Jason Gu | en_US |
dc.contributor.thesis-reader | Dr. William Phillips | en_US |
dc.contributor.thesis-reader | Dr. Jason Gu | en_US |
dc.contributor.thesis-supervisor | Dr. E. El-Masry | en_US |
dc.contributor.ethics-approval | Not Applicable | en_US |
dc.contributor.manuscripts | Not Applicable | en_US |
dc.contributor.copyright-release | Yes | en_US |