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dc.contributor.authorHammad, Issam
dc.date.accessioned2010-10-26T17:54:59Z
dc.date.available2010-10-26T17:54:59Z
dc.date.issued2010-10-26
dc.identifier.urihttp://hdl.handle.net/10222/13110
dc.description.abstractThis thesis introduces new efficient hardware implementations for the Advanced Encryption Standard (AES) algorithm. Two main contributions are presented in this thesis, the first one is a high speed 128 bits AES encryptor, and the second one is a new 32 bits AES design. In first contribution a 128 bits loop unrolled sub-pipelined AES encryptor is presented. In this encryptor an efficient merging for the encryption process sub-steps is implemented after relocating them. The second contribution presents a 32 bits AES design. In this design, the S-BOX is implemented with internal pipelining and it is shared between the main round and the key expansion units. Also, the key expansion unit is implemented to work on the fly and in parallel with the main round unit. These designs have achieved higher FPGA (Throughput/Area) efficiency comparing to previous AES designs.en_US
dc.language.isoen_USen_US
dc.subjectAESen_US
dc.subjectFPGAen_US
dc.subjectI-BOXen_US
dc.subjectComposite Fielden_US
dc.subjectFinite Fielden_US
dc.subjectCryptographyen_US
dc.subjectEncryptionen_US
dc.subjectEmbedded Systemsen_US
dc.titleEfficient Hardware Implementations For The Advanced Encryption Standard Algorithmen_US
dc.date.defence2010-10-25
dc.contributor.departmentDepartment of Electrical & Computer Engineeringen_US
dc.contributor.degreeMaster of Applied Scienceen_US
dc.contributor.external-examinerDr. William J. Phillipsen_US
dc.contributor.graduate-coordinatorDr. Michael Cadaen_US
dc.contributor.thesis-readerDr. Jason Guen_US
dc.contributor.thesis-supervisorDr. Kamal El-Sankary , Dr. Ezz El-Masryen_US
dc.contributor.ethics-approvalNot Applicableen_US
dc.contributor.manuscriptsNot Applicableen_US
dc.contributor.copyright-releaseNot Applicableen_US
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