Design of Low-Voltage Wide Tuning Range CMOS Multipass Voltage-Controlled Ring Oscillator
| dc.contributor.author | Ren, Jie | |
| dc.contributor.copyright-release | Not Applicable | en_US |
| dc.contributor.degree | Master of Applied Science | en_US |
| dc.contributor.department | Department of Electrical & Computer Engineering | en_US |
| dc.contributor.ethics-approval | Not Applicable | en_US |
| dc.contributor.external-examiner | Dr. William Phillips | en_US |
| dc.contributor.graduate-coordinator | Dr. Michael Cada | en_US |
| dc.contributor.manuscripts | Not Applicable | en_US |
| dc.contributor.thesis-reader | Dr. Jason Gu | en_US |
| dc.contributor.thesis-supervisor | Dr. Ezz El-Masry, Dr. Kamal El-Sankary | en_US |
| dc.date.accessioned | 2011-04-08T16:24:43Z | |
| dc.date.available | 2011-04-08T16:24:43Z | |
| dc.date.defence | 2011-03-23 | |
| dc.date.issued | 2011-04-08 | |
| dc.description.abstract | This thesis introduces a multipass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10222/13341 | |
| dc.language.iso | en | en_US |
| dc.subject | VCO | en_US |
| dc.subject | PLL | en_US |
| dc.subject | CMOS | en_US |
| dc.title | Design of Low-Voltage Wide Tuning Range CMOS Multipass Voltage-Controlled Ring Oscillator | en_US |