Innovative Time-Domain Approaches for High-Performance Readout Circuits

Abstract

The scaling of Complementary Metal-Oxide Semiconductor (CMOS) technology presents challenges for low-power, low-frequency sensor readout interfaces, particularly in nonlinearity, noise, and power efficiency. This dissertation explores time-domain signal processing (TMSP) to overcome these limitations, introducing two key contributions: a linearized open-loop Voltage-Controlled-Oscillator (VCO) Analog-to-Digital Converter (ADC) and a time-domain Goertzel-based frequency analyzer for low-frequency applications. The first contribution presents an ultra-low-power open-loop VCO-ADC, designed for direct digitization of low-frequency signals. A pseudo-differential transconductance, (G_M), stage linearization technique effectively suppresses even-order and third-order harmonics distortion, enhancing linearity and Dynamic Range (DR). Fabricated in 180 nm CMOS, the design achieves an Spurious-Free Dynamic Range (SFDR) of 81.48 dB, Total Harmonic Distortion (THD) of -76.8 dB, and Signal-to-Noise-and-Distortion Ratio (SNDR) of 70.9 dB (equivalent to 11.48 Effective Number of Bits (ENOB)) over a 3.6 kHz Bandwidth (BW), with low flicker noise achieved through a chopper-based noise suppression technique. The ADC operates at 1 V, consuming only 20.3 μW, making it highly efficient for low-frequency sensor readout. The second contribution introduces a time-domain Goertzel-based frequency analyzer, implemented for the first time in the analog time domain. A set of proposed TMSP arithmetic circuits, including a single-step time-register (TR) and time-amplifier (TA), enables real-time magnitude and phase extraction with less than 5% error for input frequencies up to 400 Hz. The CMOS 180 nm implementation consumes less than 24 μW, demonstrating superior power efficiency compared to conventional ADC + FFT architectures. These findings establish time-domain architectures as a scalable, low-power alternative for low-frequency sensor interfaces.