Design and Implementation of a 10-bit 50-MS/s Radiation Tolerant Split Coarse/Fine SAR ADC in 65-nm CMOS

Abstract

Integrated circuits in aerospace applications face significant reliability challenges due to exposure to harsh radiation environments, which can induce Single Event Effects (SEEs) and Total Ionizing Dose (TID) degradation. This thesis presents the design, implementation, and validation of a 10-bit, 50 MS/s Radiation-Hardened by Design (RHBD) Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) tailored for irradiation conditions. Fabricated in a standard TSMC 65-nm CMOS process, the ADC leverages multiple redundancy strategies at both system and circuit levels to mitigate radiation-induced errors and metastability. At the system level, a novel split Coarse/Fine asynchronous SAR ADC architecture is proposed, which functions as a sub-ranging system under normal conditions and provides robust system-level redundancy. This architecture is designed to detect and discard erroneous conversion bits resulting from SEEs, thereby maintaining data integrity. Circuit-level SEE error detection is achieved through a co-designed scheme incorporating Last Bit Cycle (LBC) detection, which monitors voltage jumps in the DAC, and Metastability Detection (MD) using a ramp generator and threshold trigger. These mechanisms enable the identification and correction of radiation-induced errors and metastability issues via a Coarse/Fine redundant algorithm. Sub-radix-2 DACs are employed in both coarse and fine stages to introduce inherent redundancy for error correction. The prototype RHBD SAR ADC core occupies an area of 0.0875 mm² and consumes 2.79 mW from a 1.2-V supply at 50 MS/s, achieving up to 8.78 Effective Number of Bits (ENOB). Post-irradiation tests confirm functionality up to 100 krad(Si) TID and demonstrate over 90% suppression of large SEEs (>5 LSB) under laser testing, validating the effectiveness of the combined RHBD strategies. This research extends beyond the primary ADC to investigate critical analog components. A Single Event Transient (SET), a temporary voltage pulse caused by a particle strike, poses a significant threat to circuit reliability. To combat this, this work presents a holistic radiation-hardening methodology across multiple design levels. At the system level, a novel split coarse/fine architecture provides efficient redundancy with low overhead. At the circuit level, this work incorporates a radiation-hardened Quatro-Latch comparator and Dual-Interlocked Cell (DICE) logic to mitigate SETs at their source. A comprehensive study on SETs in switched-capacitor amplifiers further led to the proposal of a novel Parallel-Auxiliary Ring Amplifier (PA-RAMP) hardening solution. In summary, this thesis offers a multi-faceted approach to the design and implementation of robust, power-efficient, radiation-hardened mixed-signal circuits, providing validated solutions for critical data acquisition systems in radiation-prone aerospace environments.