EFFICIENT AND OPTIMIZED HARDWARE IMPLEMENTATION FOR FORWARD ERROR CORRECTION (FEC) OPTICAL COMMUNICATION

Abstract

This PhD thesis focuses on developing new techniques of efficient architectural and circuit level implementation of forward error-correction (FEC) encoders and decoders for high-speeds fiber-optical communications. The proposed methods are applied to some of the most recent optical communication protocols, specifically 400ZR and open FEC (oFEC), operating at 400 GBps. The thesis presents a Soft Input Hard Output (SIHO) high-throughput hardware-friendly Hamming decoder implementation using an optimized algorithm called Direct Error Pattern Testing (DEPT). This algorithm selects candidate patterns based on a threshold level for Bit Error Rate (BER) at the output of the Hamming decoder in the 400ZR implementation. The study further includes the implementation of a staircase decoder based on inverse Peterson algorithm which was concatenated with the Hamming code to achieve a BER below 10−15. An oFEC encoder based on the oFEC agreement is implemented as a baseline, followed by a novel technique proposed to reduce memory size and hardware complexity in terms of area and power. Moreover, a soft BCH decoder based on the Chase II algorithm is proposed, utilizing a Look-Up Table (LUT) as the core of the iterative BCH decoder implementation for the oFEC code. It enables a novel function-based method which is developed for generating error positions based on the analysis on the error locations to simplify the LUT. The thesis also discusses Time Domain Signal Processing (TDSP) concepts and proposes a potential hybrid BCH decoder (combining digital and time domain approaches) for a full iterative decoder, which serves as a future plan and direction for further research.