DUAL SEGMENTED AND RECONFIGURABLE APPROXIMATE MULTIPLIERS FOR ERROR-TOLERANT APPLICATIONS

Abstract

Approximate multiplier circuit designs have shown substantial advantages in improving many operational features, such as power, area and delay, in many error-resilient applications such as image processing and deep learning applications. Existing approximate multiplier circuits in this thesis are first reviewed, evaluated, and compared. The comparison results show that the segment-based multiplier has a good trade-off between accuracy and performance by adjusting segment size. A dual segmentation approximate multiplier is then proposed. Compared to the dynamic segment method (DSM)-based approximate multiplier, the proposed design can reduce the energy by 37.90% for 32-bit multipliers, and by 16.68% for 16-bit multipliers. The DSM and proposed multipliers have almost identical accuracy. A merged approximate multiplier with two configurable precisions is proposed for improving the multiplication performance in fixed point convolutional neural networks (CNN) accelerators. Compared with the single-precision approximate multiplier, the merged approximate multiplier achieves significant performance enhancements with minimal accuracy loss.