Pipeline Implementation of AES Algorithm for Improved Resource Management and Higher Throughput

Abstract

This thesis is focused on a Field Programmable Gate Array (FPGA) based implementation of Advanced Encryption Standard (AES) cryptography. The objective is to effectively implement the AES algorithm with less resource utilization and higher throughput. A pipeline AES architecture is implemented and compared with a standard iterative architecture in this work. Performance improvement has been done in different stages. The sub bytes, shift rows, mix columns, and add round key functions of the AES are performed in a single module for each round of encryption or decryption. The critical path delay has been reduced using logical components for the sub bytes instead of using a pre-computed Look Up Table (LUT). Clock gating and timing constraints have been applied to increase the throughput and reduce the total number of LUTs, Flip Flops and Input/Output (I/O) pins used in the design. To analyze the performance of the implemented pipeline architecture, a unique task-scheduling script is developed to establish a back-to-back connection at the simulator level and to monitor the performance of the implemented digital system. The script is developed in PERL scripting language, and it fully automatizes the testing process for the total packets/bytes transmitted as well as the duration of the transmission, line rate, and packet rate. The results obtained with the simulation can be reflected on a designated computer console. This unique technique of demonstrating backend parameters has proved to be very effective in design verification of the FPGA based AES implementation. The implementation of the AES algorithm in this thesis is as per the National Institute of Standards and Technology (NIST) standard, and the pipelined architecture is synthesized using Advanced Micro Device (AMD's) Vivado synthesis Electronic Design Automation (EDA) tool. The standards and techniques used in this thesis are not limited to the scope of this thesis but can be used across many research projects for digital design and verification purposes.