CMOS Sensor front-end and Data Converters for interface readout applications

Abstract

The need for easily interfaced sensors is ever-increasing in the growing world of computers and digital systems. System performance depends more on many applications' sensors, actuators, and interface electronics. As a result, it is becoming increasingly important to develop and improve interface electronics. This thesis proposes a low-power, high-resolution, high-sensitivity analog front-end for IoT sensor node array or Biomedical Sensor, Device, and Measurement Systems. The signal measurement under very low SNR is essential for integrated readout circuits. There are various methods used to detect the signal buried under ambient noise. An integrated lock-in amplifier (LIA) with automatic phase tuning and second-order harmonic frequency extraction is presented in this thesis. The automatic phase alignment loop implemented in the proposed single-channel LIA can directly align the phases of an input signal with a reference signal. Furthermore, the proposed LIA system also includes an enhanced signal detection method in which the 2nd harmonics of the carrier frequency (𝜔𝑟𝑒𝑓) is applied. This method, unlike conventional LIA, reduces flicker noise and input offset effects that limit the signal-to-noise ratio (SNR). In terms of signal power detection, the proposed single-channel LIA architecture does not require phase synchronization between input and reference signals. The circuit is designed for a reference frequency of 100 Hz, which is suitable for biomedical applications. The LIA is implemented using 0.18-μm CMOS technology with a single power supply voltage of 1.8 V. The system consumes 360 μW at an operating frequency of 100 Hz and presents a high input sensitivity dynamic range for a detection bandwidth of 50 Hz and a FOM of 55.4 nW/Hz.