Towards Current-Mode Analog Implementation of Deep Neural Network Functions
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This thesis proposes a current-mode analog circuit design that operates in the subthreshold region to implement various Deep Neural Network functions. The implemented circuit blocks include binary weight multiplier layer, Rectified Linear Unit, and approximate Softmax layer. The proposed designs were implemented using 180nm CMOS technology with a 1.5V power supply. Furthermore, the impact of the proposed design on accuracy was simulated using the MNIST dataset. Using a four layers Convolutional Neural Network (CNN) with an 8 bits resolution, the design achieved an accuracy of 99.02% with 68.21uW power consumption, which is 35.65% lower than the existing analog DNN design.