A RECONFIGURABLE INTEGRATED RECEIVER FRONT-END FOR HETEROGENEOUS UNDERWATER SENSOR NETWORKS

Abstract

With the increased interest in the Internet of Things (IoT), more and more sensors are implemented to satisfy the demand of various applications. In this project, a low power, controllable, high-resolution sensor node relying on a delta-sigma analog to digital converter (ADC) is introduced for IoT applications, and more speci ally to enable underwater communication networks that rely on the low frequency of operation.

Typically, remote sensors are not required to process the data and they act like relays. As such, those sensors normally require small footprints, low power consumption, narrow bandwidth, and are architecturally simple. In this research, a receiver design is proposed and operates in the acoustic and ultrasonic bands. It is intended to be a relay for underwater monitoring, and the device can also be applied for example as a sensor in a security system, or in other acoustic and ultrasonic remote control systems. In this design, three key components are described: 1) an inductor-less voltage controlled oscillator, 2) a channel acquisition filter and 3) a continuous-time (CT) Delta Sigma modulator (DSM) ADC. The three designs are implemented in TSMC's 65-nm CMOS technology.

The proposed active inductor (AI) based VCO has already been designed and fabricated. The proposed AI-VCO is compact, has a wide linear tuning range, consumes low power, and exhibits good phase noise performance. It achieves an excellent figure of merit (FOM) around -163 dBc/Hz in comparison to previous designs. The proposed gm-C based channel selection filter is currently finished the design and measurement. The fi lter can achieve a wide passband range from 60 kHz to 2.5 MHz with an almost constant Q-factor equal to 7.2. The power consumption of this fi lter is only a few microWatts excluding the digital control cell. Finally, a 4th-order CT DSM provides high resolution, less active components, and a hybrid structure compared with existing solutions. A single amplif ier biquad (SAB) integrator, a passive integrator, and a first-order integrator are used for the low-pass CT DSM. The proposed design can realize a 2 MHz bandwidth with an OSR equal to 50. The peak SNR and an effective number of bits (ENOB) of the proposed design is 82.3 dB and 12.8 bits respectively.