Low-Power Staircase Encoder Implementation for High-Throughput Fiber-Optical Communications
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This thesis presents a very large scale integration (VLSI) architecture of a high-throughput, low latency and power staircase forward error correction (FEC) encoder. The designed encoder achieves low latency and memory overhead by splitting the parity generation matrix and pre-computing partial parity bits for the next staircase block while generating the current staircase block. The proposed encoder is designed with multistage pipelined architecture that enables high efficiency in terms of throughput and area. The proposed staircase encoder was synthesized using 65nm CMOS technology. The throughput of the encoder achieves 432Gbps when operating at 909MHz, with the power consumption of 323mW.