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dc.contributor.authorSandhu, Tejinder Singh
dc.date.accessioned2019-11-28T16:48:15Z
dc.date.available2019-11-28T16:48:15Z
dc.identifier.urihttp://hdl.handle.net/10222/76710
dc.description.abstractReduced voltage dynamic range and increased mismatch between identical circuit components become pressing challenges as the transistor dimensions enter the nanometer scale. Recently, through silicon via (TSV) technology allows diverse analog and digital dies to be stacked vertically forming a compact three-dimensional integrated circuit (3D-IC). Yet, enhanced system integration in 3D-ICs comes at the cost of increased mismatch resulting from TSV defects and worsening thermal gradients when compared to their 2D counterparts. This thesis presents mismatch insensitive circuit design techniques for two applications including differential voltage to time converters and digital clock distribution architectures for 3D-ICs. This thesis purposes a mismatch insensitive skew compensation (MISC) architecture for 3D-ICs that can align a source clock in die-1 with a load clock in die-2 regardless of control code dependent mismatch between delay lines or defect induced delay disparity in TSVs. Additionally, an on-chip auto-tuning algorithm to reduce the supply voltage sensitivity of delay lines utilized in MISC is presented. This supply compensated MISC architecture is fabricated in 65nm CMOS and occupies 0.016mm2 while dissipating 4.8mW at 1GHz from a 1V supply. The maximum residual skew between the die-1 and die-2 clocks measures under 30ps for up to 50% mismatch in delay lines and up to 1ns delay disparity between TSVs. The rms jitter of this supply compensated MISC design measures 3.0ps in the presence of a 25mV 1MHz supply noise at 1GHz operation, compared to 112.3ps for the conventional design. Additionally, beyond rail-to-rail (BR2R) compliant cascode current sources that can linearly charge a load capacitor to beyond the supply rails Vdd or gnd while maintaining an improved output impedance over an equivalent wide-swing cascode source are purposed. A mismatch insensitive differential voltage to time converter (DVT) employing these BR2R sources is fabricated in 65nm CMOS and dissipating 47µW at 1V. The measured BR2R DVT SNDR is 50.2dB, compared to 38.7dB for the wide-swing cascode based DVT within a 2MHz input bandwidth. The DVT achieves a CMRR of 35.1dB for a 0.4V to 0.6V input common-mode range.en_US
dc.language.isoenen_US
dc.subjectMicroelectronics Engineeringen_US
dc.subjectMixed Signal Circuit Designen_US
dc.subjectIntegrated Circuitsen_US
dc.titleMISMATCH INSENSITIVE VOLTAGE TO TIME CONVERSION AND CLOCK DISTRIBUTION TOPOLOGIES FOR THREE DIMENSIONAL INTEGRATED CIRCUITSen_US
dc.date.defence2018-09-24
dc.contributor.departmentDepartment of Electrical & Computer Engineeringen_US
dc.contributor.degreeDoctor of Philosophyen_US
dc.contributor.external-examinerDr. Mourad N El-Gamalen_US
dc.contributor.graduate-coordinatorDr. Dmitry Trukhacheven_US
dc.contributor.thesis-readerDr. Jason Guen_US
dc.contributor.thesis-readerDr. William Phillipsen_US
dc.contributor.thesis-supervisorDr. Kamal El-Sankaryen_US
dc.contributor.ethics-approvalNot Applicableen_US
dc.contributor.manuscriptsYesen_US
dc.contributor.copyright-releaseYesen_US
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