Digital Communications Combined Frame Detector and Carrier Frequency Offset Estimator
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This thesis describes a flexible digital logic design which allows a communications receiver to synchronize with a data frame and estimate its frequency offset using only its cyclic prefix and tail data. The design is implemented as digital logic running on a field-programmable gate array which controls a software defined radio as a testbed. Synchronization reliability is improved using a finite state machine which locks-on to a received signal and falls-out-of-lock in noise. The state machine reliability is calculated using Markov chain analysis. The frequency offset is estimated using a custom complex argument function which does not use a small angle approximation. When run on the testbed, the design successfully provides synchronization and a frequency offset estimate using only the received data's cyclic prefix and tail data.