SOFT ERROR TOLERANT DESIGN OF STATIC RANDOM ACCESS MEMORY BITCELL

Abstract

Static Random Access Memories (SRAMs) are commonly used in most of electronics. Due to the scaling of silicon technologies, the soft errors induced by energetic particles are becoming a significant reliability concern. This thesis presents two new Radiation-Hardened-by-Design (RHBD) bitcell designs for SRAMs. The effectiveness of the proposed RHBD bitcell designs are evaluated by using Simulation Program with Integrated Circuit Emphasis (SPICE) and Technology Computer Aid Design (TCAD) tools. The designs are implemented using Taiwan Semiconductor Manufacture Company (TSMC) 65 nm technology, and are validated in three different radiation experiments (alpha, proton and heavy ion particles). This thesis has thoroughly introduced the SRAM bitcell topology, layout design, SRAM peripheral circuits, SPICE simulation, TCAD simulation and radiation experiments. The comparison of simulation and experimental results are clearly made. The thesis has presented designs which are more soft error tolerant in certain Linear Energy Transfer (LET) ranges compared to the reference bitcells.