A Self-Healing Technique Using ZTC Biasing for PVT Variations Compensation in 65nm CMOS Technology
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This thesis proposes a digital oriented self-healing technique in 65nm CMOS technology for current sources by biasing the current reference transistor in the vicinity of the Zero Temperature Coefficient (ZTC) point. This method, utilizes MOSFET self-heating in order to determine bias point position with respect to the ZTC point and converge the bias point to the vicinity of the ZTC point. As the result, process, voltage, and temperature are compensated for significantly. The ZTC point existence in 65nm scale has been proven to exist below the nominal supply voltage. A circuit level modeling of the effect of self-heating and current change with temperature is proposed in this work to allow the simulation of the circuit using transient analysis in the Spectre simulator environment. The proposed self-healing circuit is applied to current sources biasing two common analog and digital applications and the simulation results of the self-healed applications are discussed.