Digital Calibration and High-Speed Envelope Detector for Super-Regenerative Receiver

Abstract

In this thesis, a high-speed RF envelop detector (ED) and a blind background calibration of super-regeneration receiver (SRR) are presented. The proposed ED uses a dynamic load (DL) technique with class-AB architecture to achieve high speed by adjusting the output impedance adaptively. To improve linearity and the key specifications of ED, a derivative superposition (DS) technique is employed. A bulk-compensated technique is proposed to reduce process-voltage-temperature (PVT) variations in the proposed ED. The bulk-compensated technique constructs a ‘detecting-feedback’ loop and achieves effective compensation for PVT variations of MOS transistors through bulk potential modulation. The bulk-compensated class-AB inverter is implemented in 0.18 um CMOS process. Compared to uncompensated class-AB ED, the sensitivity of the proposed ED to process variation is greatly reduced under PVT variations. Also, a blind background calibration architecture is proposed and designed to help the SRR to maintain its high sensitivity and immunity to negative transconductance variations under process-voltage-temperature (PVT) variations. The simulation results successfully verify the reliability of the proposed calibration technique and result in significant improvements for SRR sensitivity under different process corners.