Elsalahati, Tamer2017-12-152017-12-152017-12-15http://hdl.handle.net/10222/73527A design technique for an asynchronous Analog-to-Digital Converter (ADC) is presented. The proposed design retains a clockless level crossing sampling technique, and then applies a Wavelet Neural Network (WNN) technique. High-level simulation results are shown for various ADC resolutions. The Signal to Noise and Distortion Ratio (SNDR) achieved for 4-bit ADC systems are presented. It has been shown that a 4-bit system with the proposed asynchronous ADC architecture using a WNN technique achieves an Effective Number Of Bits (ENOB) of up to 38 bits depending on the input frequency and resolution.en-USQuantization (signal)Neural networksWavelet transformsDelta modulationSignal resolutionWavelet Neural NetworksContinuous TimeClockless ADCLevel Crossing ADCThesis