Performance Analysis of Cryptographic Functions on Programmable NICs

Abstract

The development of programmable network interface cards (also known as SmartNICs) often come with multiple computing cores and multi-hundred Gbps bandwidth that can be used as an enhancement of network computing to extend the server CPU processing capacity. This trend inspired academics and industry to put more roles on the SmartNICs for applications offloading or acceleration that can traditionally only run on the servers (e.g., key-value stores or distributed transactions). However, there are no systematic studies on running network security applications on the SmartNIC, especially those commonly incorporated with heavy-loaded cryptographic operations. This thesis aims to fill the gap by providing the first in-depth analysis of the cryptography capabilities of the current SmartNICs. Our study shows that the SmartNICs' cryptographic performance is highly influenced by cryptographic instructions optimization, crypto-hardware acceleration, and other architectural enhancement. Moreover, data transmissions between SmartNICs and their onboard crypto-hardware accelerator can impact the overall cryptographic performance, especially for small-size short-living tasks. However, SmartNICs can take advantage of their deployment location, i.e., closer to client devices than server CPUs, to speed up crypto-based functions, especially for latency-critical applications. However, the SmartNIC benefits can be easily outweighed if the application is too data-intensive or includes several non-crypto tasks.