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dc.contributor.authorParmar, Shivani
dc.date.accessioned2017-09-01T18:23:30Z
dc.date.available2017-09-01T18:23:30Z
dc.identifier.urihttp://hdl.handle.net/10222/73285
dc.description.abstractA fully digital Time Domain Multiplier (TDM) has been proposed in this thesis for application in time domain signal processing. The Time Domain Multiplier presented in this work is based on the principle of repetitive addition. The TDM block consists of time adder, GRO, counter and a time register circuit. The time register serves as the core of the TDM implementation. The time register has been used to add two time-domain signals as well as to store them during the feedback. The implementation of TDM is done using 65 nm process technology at 1.2 volt. During the simulation, the maximum error was found in between -9 ps to 11 ps. The maximum error at 1X multiplication was -1.4ps, at 2X multiplication -5aps and at 3X multiplication 11ps. The circuit has been designed with a target application in signal processing operations such as filtering and Fast Fourier Transform (FFT).en_US
dc.language.isoen_USen_US
dc.subjectTime domain multiplicationen_US
dc.titleFULLY DIGITAL TIME DOMAIN MULTIPLIERen_US
dc.typeThesisen_US
dc.date.defence2017-08-25
dc.contributor.departmentDepartment of Electrical & Computer Engineeringen_US
dc.contributor.degreeMaster of Applied Scienceen_US
dc.contributor.external-examinerDr. William phillipsen_US
dc.contributor.graduate-coordinatorDr. Jason Guen_US
dc.contributor.thesis-readerDr. Jason GUen_US
dc.contributor.thesis-supervisorDr.Kamal El Sankaryen_US
dc.contributor.ethics-approvalNot Applicableen_US
dc.contributor.manuscriptsNot Applicableen_US
dc.contributor.copyright-releaseNot Applicableen_US
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