FULLY DIGITAL TIME DOMAIN MULTIPLIER
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A fully digital Time Domain Multiplier (TDM) has been proposed in this thesis for application in time domain signal processing. The Time Domain Multiplier presented in this work is based on the principle of repetitive addition. The TDM block consists of time adder, GRO, counter and a time register circuit. The time register serves as the core of the TDM implementation. The time register has been used to add two time-domain signals as well as to store them during the feedback. The implementation of TDM is done using 65 nm process technology at 1.2 volt. During the simulation, the maximum error was found in between -9 ps to 11 ps. The maximum error at 1X multiplication was -1.4ps, at 2X multiplication -5aps and at 3X multiplication 11ps. The circuit has been designed with a target application in signal processing operations such as filtering and Fast Fourier Transform (FFT).